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If WR_BE_RDY has been continuously asserted and is deasserted, two additional writes to the backend may occur. To
avoid these extra writes, the backend should only assert WR_BE_RDY for a single cycle and should not reassert it until
the write takes place (WR_BE_NOW is asserted). These additional writes are shown in Figure 6-13 in cycles 8 and 9.
cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
clk
framen
ad[31:0]
ADDR
0
1
2
3
cben[3:0]
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
wr_cyc
wr_be_rdy
7
0
0
wr_be_now[3:0]
F
0
F
mem_add[15:0]
0000
0004 0008
000C
mem_data_out[31:0]
0
1
2
3
Figure 6-13 · Backend Burst Write Cycle with Additional Writes after Ready Removed
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